Audio D/As typically consist of four processing elements. First the input audio data is filtered with an interpolation filter to remove out-of-band images. Then a sigma-delta modulator processes the interpolated data to produce a digital bit stream suitable for conversion into an analog signal. That bit stream is passed to a D/A, whose output is input to an analog filter to recreate an accurate representation of the music signal (Fig. 1).

While it is extremely difficult to make a 16- to 24-bit non-delta-sigma D/A, one advantage of such an approach is the low out-of-band noise. However, if such a device operates at a low rate (approaching the Nyquist rate for the signal), e.g., 44.1 kHz and 48 kHz for audio signals, the output spectrum will contain strong image components. The solution is to use an interpolating filter to increase the sample rate without significant images.

The first delta-sigma-modulator-based audio D/As were predominantly single-bit designs. The reason was that with only two levels to implement, any errors in the reproduced D/A levels manifest as gain and offset errors and do not affect the linearity and noise performance of the overall system.

In the case of a one-bit D/A, the filter must be capable of transforming this stream of pulses into a real-world analog waveform, not an easy task. Furthermore, the one-bit converter is sensitive to clock jitter (Fig. 2). Jitter in the oversampling clock translates directly into D/A errors causing gross errors, increasing noise and thereby reducing the sound quality of audio D/As.

More recently, it has become common to combine delta-sigma modulation with a multilevel D/A with a modest number of output levels to provide an improvement in out-of-band noise and signal images. Out-of-band energy is undesirable since it can result in audio band components due to nonlinearity in the system at high frequencies.

A multibit sigma-delta D/A is constructed using multiple two-level D/As (Fig. 3). Outputs are summed to provide an analog output and a scrambler selects appropriate combinations of D/A outputs for good linearity. Output from the D/A now looks more like an analog signal; it becomes a relatively easy task to effectively filter the output. The use of a multibit D/A also accounts for the insensitivity of such devices to clock jitter, thus resulting in better sound quality.

The PCM (pulse-code modulated) input signal has its sample rate increased using an interpolation filter to attenuate the image components. The high sample rate signal is then delta-sigma modulated to reduce the number of levels used. This introduces additional quantization noise, but the operation of the delta-sigma modulator feedback loop ensures that very little additional noise is introduced over the audio bandwidth. If the delta-sigma modulator produces a single one-bit output signal, this may then be fed directly into a one-bit D/A. However, it is better to retain a few bits of resolution at the delta-sigma output to reduce the out-of-band noise.

If a conventional multibit D/A is used, any errors in the reproduced analog levels contribute to in-band noise and distortion, placing unrealizable tolerances on the analog components. To overcome this, the multibit signal is processed further to decompose it into a number of individually delta-sigma modulated signals, the sum of which provides the output. This process is called dynamic element matching (DEM) since it lessens the required matching accuracy of the D/A elements1. Each of these signals has the characteristics of a single-bit delta-sigma modulated signal. The two-level DEM system outputs are used to control how D/A elements are selected. The combination of a two-level signal and D/A element may be considered to be a two-level D/A. The output of the complete D/A system is then the sum of all the two-level D/A outputs.

Most such multilevel D/A schemes employ equally weighted unit elements. For example, a five-bit converter will have 31 or 32 unit elements. The DEM schemes that are commonly used only work for equally weighted elements. This limits the number of bits before the number of individually controlled unit elements becomes unmanageable. A method for increasing the number of D/A levels without significantly increasing the number of controlling signals is described below.

In the one-bit D/A converter, clock jitter inthe over sampling clock translates directly into D/A errors - causing gross errors, increasing noise and reducing the sound quality.

In a multibit sigma-delta made up of multiple two-level D/A converters, the D/A output looks more like an analog signal, making it less sensitive to jitter and easier to filter.

We designed the digital filter providing an acceptable performance-to-cost compromise in parallel with the rest of the digital signal path, including the multibit sigma-delta modulator. Degrees of freedom in the modulator include the order of the sigma-delta modulator, the number of bits in the multibit D/A, the type of DEM scheme used and the design of the analog components used to implement the D/A itself. The complete signal path from serial audio interface, through the digital filter, into the sigma-delta modulator and finally through the multibit D/A DEM scheme is then simulated using Wolfson proprietary modeling tools.

These tools are written in C++, allowing fast simulation. This is important in order to perform the lengthy simulations needed to determine performance of the circuit in an acceptable time. Typically, to generate plots showing sweeps of, for example, signal-to-noise ratios vs. amplitude, many thousands of time domain simulations must be run and a signal-to-noise ratio calculation performed for every one. Attempting to perform the large number of time domain simulations needed to fully analyze the circuit using typical digital simulation tools would take an unacceptable amount of time. These simulations are performed at a bit-accurate level, using models of the circuits that represent close to the gate-level representation of the chip. This allows simulation results to be gathered; they are later compared with the actual gate-level implementation of the circuits.

Once the design of the digital processing elements has been completed at this C++ model level, the circuits are implemented at the gate level. This is typically done with a mixture of Verilog and schematic level-driven design approaches, depending upon the function of the particular circuit. Once the circuits have been implemented at the gate level, the resulting designs are synthesized and a gate-level netlist is produced. This netlist can then be simulated using commercial Verilog (or similar) simulation tools and the results compared bit for bit with the output from the C++ model-generated simulations. These digital simulations include models within them for the switched capacitor D/A functions and therefore allow simulation of the complete chip, from serially input audio data right through to analog output waveforms. The bit-for-bit comparison of the output results from these simulations to those created using the C++ model-based simulations gives a high degree of confidence that what is built in gates will actually perform as expected based on the higher-level simulation results.

The analog domain circuits are simulated using Spice-type tools. Results from the digital simulations are converted into Spice format piecewise-linear waveforms and submitted as input to the Spice netlist of the analog circuits. Typically, time domain simulations of full-scale maximum frequency sine waves will be simulated; then the resulting analog waveform will be analyzed using Fourier analysis to check for acceptable distortion.

A significant benefit gained from performing these end-to-end simulations is that every wire, every connection, every gate and transistor on the chip is fully simulated, so the likelihood of top-level chip wiring errors is minimized and confidence of achieving expected levels of performance is maximized.

We use proprietary techniques to ameliorate the impact of using a multilevel D/A with a low-order modulator. These are described below.

The idea behind all DEM techniques is to decompose a digital input sequence into a number of output sequences that are used to drive multiple D/As whose outputs are summed to provide an analog output, as shown in Figure 1. The sum of these output sequences is always equal to the input sequence at every sample instant. Each output signal can take on only two levels, which are used to determine how a particular D/A element is used (either use/not use or use in a positive/negative sense). The two-level output signals are arranged to have a frequency spectrum that has little power at low frequencies other than that associated with the input signal. This results in reduced errors at low frequencies when the D/A elements have errors from their nominal values. In particular, linearity is improved since particular D/A elements are not used predominately for any particular set of input values-each D/A element is used with approximate equal frequency as any other in the system, for any input sequence.

We have developed a novel approach to tackle the problem of rapidly increasing circuit complexity vs. number of bits in the multibit D/A approach used in conventional DEM schemes. In an equally weighted pattern, the number of D/A elements increase as 2 to the power of the number of bits. But Wolfson uses a binary weighted array of D/A elements, producing an increase in the number of D/A elements linearly proportional to the number of D/A bits.

Clearly, the "shuffling" system typically used in conventional DEM schemes can no longer be used when the D/A elements are binary weighted in value, so an alternative plan is needed. In this case a solution has been developed comprising a cascaded binary weighted array of vector-coupled sigma-delta modulators,2 where each stage of the multibit array comprises a pair of single-bit delta-sigma loops. Thus, each bit in the multibit binary weighted array comprises a pair of one-bit D/As, each noise shaped by the first-order single-bit delta-sigma modulator. The total number of D/A elements is therefore 2 x n, where n is the number of bits in the multibit D/A.

Noise shaping in each of the binary weighted stages causes noise from capacitor mismatches in the binary weighted array to be noise-shaped, thus minimizing degradation of the in-band performance. The end result is a very area-efficient implementation of the multibit noise-shaped D/A, which has ready potential for extension to more bits with the attendant further increases in performance.

The D/A is configured as a switched capacitor filter to further reduce out-of-band noise. Another advantage of the multilevel D/A-filter combination is that the output has minimal change from sample to sample, which reduces the sensitivity to clock jitter.

D/A evaluation
Measured results from the D/A are shown in Figures 4 and 5. Figure 5 shows the wideband output spectrum at the device outputs without any off-chip filtering. Additionally, the images around 8 Fs (384 kHz) are seen to be much reduced due to the use of a linear interpolator rather than a sample-and-hold.

Typically, audio D/A specifications include signal to noise plus distortion (Sinad) for a full-scale signal and the dynamic range (measured for a -60-dB input signal). These individual numbers cannot be extrapolated to determine the performance for other input signals and do not give any indication of whether the error is correlated to the signal (harmonics), or has noiselike properties, or is concentrated at certain frequencies unrelated to the desired signal frequency (tones). Ideally the error signal should be noiselike with characteristics that do not change with input signal. Tonal-type errors must be avoided since the ear is particularly adept at picking out tones from background noise.

A graph of background noise vs. swept ac level can indicate tonal problems if the background noise level varies. Most papers on DEM contain many plots of SNR vs. signal level. Often these graphs show that most of the degradation occurs for input levels around -60 dB, but do not give any indication as to why this should occur. However, by using a dc sweep to first identify regions of the input range that have poorer noise, it is possible to track down and improve or eliminate these sources of noise.

Rather than sweeping ac amplitude, it is more illuminating to sweep the dc level slowly and to measure the in-band ac noise power. Ideally, this will be a flat line indicating that the noise characteristics are independent of the signal level. However, in the presence of element-matching error, significant peaks will occur around certain dc levels, effectively giving a signature of the particular type of dynamic element matching used and the effectiveness of any dithering applied.

With regions of poorer performance identified, either by simulation or measurement, steps can be taken to improve the performance. Often there is a region around midscale where the performance can be significantly degraded because of cycling patterns forming either in the delta-sigma modulator or in the DEM system. With no dc input, the modulator may idle between two codes, e.g. 0,1,0,1,0,1,0,1, etc. When a small positive dc offset is introduced, additional 1's must appear in the sequence occasionally. If the dc offset is small enough and the system not randomized enough by dither, then it is likely that the additional 1's will appear at almost regular intervals giving rise to a tone. If the dc level is increased, the additional 1's will appear more often, causing the tone to rise in frequency and power level. Further increases in dc level cause the tone frequency to go outside the measurement bandwidth (usually 20 kHz) with the result that the in-band noise/tone power improves. This phenomenon occurs symmetrically, giving a pair of noisy regions that are centered on midscale. The performance degradation that is often seen at about -60 dB is due to this effect-at this level the peaks of the sinusoidal signal fall in the regions with poor performance. Larger signals occupy less time in the noisy regions, and smaller signals lie in the null between the pair of noisy regions around midscale.

A similar argument applies to the standard rotating DEM scheme with a component mismatch. A small dc offset causes the element selection pattern to slowly rotate, and with a component mismatch a low frequency tone can occur. Again, this may be alleviated by use of a dc offset, dither, or higher-order modulation.

The in-band noise-modulation test can be quite time consuming. Many hundreds or even thousands of points are necessary to be sure of catching all of the very narrow features. Thus, this method is appropriate for device evaluation and characterization but not for production test. It is also suitable for comparing different DEM methods and the effects of dither by simulation. Equivalent testing techniques may be applied to delta-sigma A/D converters with similar benefits.

The result of this dc sweep for the WM8740 can be seen in Figure 6. This graph is very flat, with very small peaks visible, compared with a sigma-delta D/A from another supplier (Fig. 7).

Data such as this demonstrates the advantages in out-of-band noise and in superior in-band noise modulation using the Wolfson architecture. Using a dc sweep test to characterize the dependency on the input signal for the noise and tonal power shows how the Wolfson D/A achieves a noise power spectrum that changes little with input level, resulting in perceptible improvements in sound output quality.

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References
1 [Norsworthy] S. Norsworth, R. Schreier and G.C. Temes (Editors), Delta-Sigma Data Converters, IEEE Press, New Jersey, 1997.

2 [Schreier & Zhang] R. Schreier and B. Zhang, "Noise-shaped multibit D/A converter employing unit elements," Electronics Letters., vol. 31, no. 20, pp. 1712-1713, Sept. 1995.